[libre-riscv-dev] daily kan-ban update 29jun2020

[Luke Kenneth Casson Leighton]

yesterday:

* wrote a new FSM-based version of Pi2LSUI after separating out the
FSM into PortInterfaceBase
* got instruction reading working from a similar runtime
configureable/selectable memory over FetchUnitInterface

this morning:

* got instructions reading from a wishbone-based harry ho SRAM over
BareFetchUnitInterface

so now we have both instructions and data reading from 64-bit wishbone
buses.  putting caches into place is a simple enough task, the only
thing being we need byte-level read/write lines and it needs to be 64
bit preferably 128 bit wide.

rest of today: not sure.  there's error handling to add (exceptions),
traps to do, the DIV unit to do, and MUL.

l.