[libre-riscv-dev] daily kan-ban update 29jun2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Jun 29 12:06:22 BST 2020
* wrote a new FSM-based version of Pi2LSUI after separating out the
FSM into PortInterfaceBase
* got instruction reading working from a similar runtime
configureable/selectable memory over FetchUnitInterface
* got instructions reading from a wishbone-based harry ho SRAM over
so now we have both instructions and data reading from 64-bit wishbone
buses. putting caches into place is a simple enough task, the only
thing being we need byte-level read/write lines and it needs to be 64
bit preferably 128 bit wide.
rest of today: not sure. there's error handling to add (exceptions),
traps to do, the DIV unit to do, and MUL.
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