[libre-riscv-dev] daily kan-ban update 28jun2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Jun 28 21:20:02 BST 2020

On Sun, Jun 28, 2020 at 4:57 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> that, and i feel that instruction reading from a wishbone bus is a
> slightly higher priority.

that's now done for a TestMemory, using minerva FetchUnitInterface.  i
had to do a fudge where 64-bit instructions are read twice, using bit
2 of the PC to select which 32-bit word from the 64-bit fetch is the

tomorrow i'll do the bare wishbone fetch, as well as do a one-line
cache of the 64-bit instruction (to stop doing two reads).  after
that, we'll be able to actually connect up litex.  L1 caches can be
dropped in when convenient.


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