[libre-riscv-dev] daily kan-ban update 28jun2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Jun 28 16:57:22 BST 2020

On Sun, Jun 28, 2020 at 4:42 PM Yehowshua <yimmanuel3 at gatech.edu> wrote:
> But still nothing on the Minerva cache I’m guessing?

that's a simple matter of adding an extra configuration here:

line 18 is currently commented-out.  it's a simple matter of creating
a cookie-cut version of the BareLoadStoreUnit test and creating a
CachedLoadStoreUnit one instead, linking up the harry ho SRAM instance
onto the "main" memory bus.

i expect it to work straight away: the only caveat being that if there
is a 2-cycle delay (because a cache miss results in the request being
retried on the "main" memory bus) there *might* be some niggles,

the reason i haven't tackled it yet is because it needs some
code-morphing to set up the parameters (size of cache etc.), and i
wanted the "simple" cases working first.

that, and i feel that instruction reading from a wishbone bus is a
slightly higher priority.


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