[libre-riscv-dev] AMD ISAs

[Luke Kenneth Casson Leighton]

On Wed, Jun 10, 2020 at 1:59 AM Yehowshua <yimmanuel3 at gatech.edu> wrote:

> > Also, that would defeat the purpose of a lot of what we're implementing
> > with a Power compatible ISA, having the CPU and GPU be the same processor,
> > and having an extensible design such that someone could add their own
> > custom operations on top of our code if they wanted.
>
> Noted. Well, it was an interesting idea while it lasted.

it's worth going over.  in a similar way, we exhaustively evaluated
different ISAs to consider: MIPS, OpenRISC1200, and so on.  AMDGPU did
have the advantage of MIAOW being a subset implementation of that ISA:
still as you can see it's not enough, because of the strong
simplification advantages of a hybrid CPU.

l.