[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Jun 1 20:31:18 BST 2020


--- Comment #5 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> michael, i need your help, here: sraw "works" in
> shift_rot/test_pipe_caller.py
> only because carry isn't being checked in the test.  i'm not sure if it's
> being set in the simulator?

>     s <- (RS)[32]
>     RA <- r&m | ([s]*64)& ¬m
>     carry <-  s & ((r&¬m)[32:63] != 0)
>     CA    <-  carry
>     CA32  <-  carry
> Special Registers Altered:
>     CA CA32
>     CR0                    (if Rc=1)

Hmm. So the way carry gets set currently in test_pipe_caller.py is that it
completely ignores modifications to the carry flag from the pseudocode and
instead updates it based on the inputs and outputs. This is because for the
arithmetic instructions (add/sub with carry), they don't actually set the carry
flag in the pseudocode. However, it seems that the shift instructions do have
pseudocode explicitly setting CA and CA32. I think parser.py should do
something to instruction_info to tell caller.py to use the carry flag from the
instruction globals and not generate one from the inputs and outputs. What
would be the best way of going about this, does it fit with one of the existing

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