[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=339

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #5)

> carry flag in the pseudocode. However, it seems that the shift instructions
> do have pseudocode explicitly setting CA and CA32. I think parser.py should
> do something to instruction_info to tell caller.py to use the carry flag
> from the instruction globals and not generate one from the inputs and
> outputs. What would be the best way of going about this, does it fit with
> one of the existing fields?

it appears to be a special case, just for sraw etc.

i would be inclined to suggest allowing CA and CA32 to be picked up as output
parameters then if spotted in the outputs the values put into corresponding XER
fields.

otherwise we need to do some messing about.

although... when i looked at the pseudicode it looked very much like it was
simply doing 32 bit carry i.e. bit 31 was detected as sign then 32 and above
nonzero is "carry".

-- 
You are receiving this mail because:
You are on the CC list for the bug.