[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Jun 12 14:31:43 BST 2020


--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
from discussion at

action points (edit and add as appropriate):

* to make a decision as to what top level of visual performance is needed
(maximum resolution, maximum framerate)
* calculate the framebuffer data transfer rate for that.
* to decide some top level of GFLOPs and MTriangles/sec (and other waffly
figures for the GPU side)
* estimate the memory bandwidth for the GPU side
* decide if we want to develop a hardware compression algorithm between memory
and framebuffer (an augmentation of Richard Herveille's RGBTTL framebuffer RTL)
* find out the power consumption in 45nm for these SERDES
* talk to Rudi to see if he can do a SERDES PHY for us
* talk to SymbioticEDA likewise
* talk to Dmitri from LIP6.fr to see what he can do, whether a stable 50 GHz
clock is achievable in 45nm (i understand from Dmitri that for a given target
clock - 25 gbit/sec in this case - you need the PLL to do double the clockrate)

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list