[libre-riscv-dev] daily kan-ban update 03jun2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Jun 3 13:50:07 BST 2020


* fixed MultiCompUnit FSM for case when there are no registers to
write (branch conditional)
* worked with Michael on Branch, deciding where to put the incoming
SPR registers (port1, port2)
* sorted out regspecs, in particular the "fast" regfile (CTR, MSR, CIA, TAR, LR)
* created a special strategic function that encodes the relationship
between regspecs, PowerDecode2, and the Function Units
* reorganised the */test_pipe_caller.py and test_*_compunit.py unit
tests to share common functions for setting up input
* worked with Cole on TRAP pipeline.
* moved RS to pipeline input position 1, in MTSPR and MTMSR.


* more pipeline / compunit test reorganisation
* dynamic enable/disable carry-in and XER flags (and test it's ok)
* remove pipe_data.py rdflags() and use strategic function
regspec_decode() instead


* continue helping Cole with TRAP pipeline
* slowly work towards linking pipelines to regfiles, now that
regspec_decode can express the port read/write characteristics, purely
from pipeline specifications (pipe_data.py)


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