[libre-riscv-dev] libresoc memory architecture
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Jun 23 22:08:03 BST 2020
On Tuesday, June 23, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Tue, Jun 23, 2020 at 9:02 PM Michael Nolan <mtnolan2640 at gmail.com>
> > On 6/23/20 3:52 PM, Luke Kenneth Casson Leighton wrote:
> > > question: where do the PowerISA MMU tables get the information from
> > > which bits are IO, RAM, or other?
> > >
> > > answer: they come from the information about the physical memory map.
> > Wouldn't they come from the software that sets up the page tables?
plus, the implications are that the hardware enforcement of the address
checking would come from the pagetable, which would make the address
range checking critically dependent on the MMU.
which we don't have yet.
and we would not be able to verify any RTL *until* we had that MMU written.
and in real mode (kernel) where access is physical and does not go via an
MMU it would mean that we had to be extremely careful and potentially limit
memory accesses to single atomic LD/ST
it all points towards having this really quite single address-check
hierarchy in hardware.
the DRAM one ... no, actually *any* peripheral that involves access to
memory addresses (LPC, FlexBus, 8080 bus, etc) all those will be a leetle
more complicated as the "valid range" will depend on the physical external
device that is connected.
that may have an effect on performance.
DRAM is safe to say it cannot be upgraded without a reboot. other
peripherals we likely just have to fall back to atomic single LD/ST.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
More information about the libre-riscv-dev