[libre-riscv-dev] daily kan-ban update 14jun2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jun 14 18:12:38 BST 2020
* did more investigation of LD/ST. added memory dump to qemu sim
* had a really nice chat with Cole.
* sorted out LD/ST by assuming qemu was correct, then correcting the
simulator to match it, then correcting the hardware to match *that*.
rest of today:
* add in LD/ST Comp Unit tests into simple/core.py and in to the "big"
tomorrow can consider adding in the InstructionQ (probably only 1
wide) and then add Minerva instruction "read" (I-Cache). have to
create some sort of nmigen-wishbone-to-Memory bridge to do that.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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