[libre-riscv-dev] daily kan-ban update 13jul2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Jun 13 15:48:50 BST 2020
* investigated LDST memory byte order discrepancy.
* reviewed proposed 40/45nm ASIC and found its interfaces to be
unachievable (25GBit/s is not practical in 45nm)
the review occupied the entire day and consequently no code was written.
continue investigating byte order particularly of simulator vs qemu in
order to be able to get it right for the hardware.
what i do not understand - what concerns me greatly - is that the simulator
appears to be storing data from the opposite (big) end of its 8 byte
granularity, computing shiftmasks based on subtracting from 8.
this would tend to suggest a hardcoded dependency on a 64 bit memory width
however reviewing both microwatt and pearpc i find no evidence of that,
hence my concern.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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