[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=216

--- Comment #58 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
worked out that this:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/wishbone.py;hb=HEAD

is exactly what we need to do the arbitration of odd/even dual ports.
actually there could be four 64-bit wishbone buses, each seeking
arbitration onto the one 64-bit memory bus:

* LSB 64-bit half of the 128-bit ODD L0CacheBuffer Port interface
* MSB 64-bit half of the 128-bit ODD L0CacheBuffer Port interface
* LSB 64-bit half of the 128-bit EVEN L0CacheBuffer Port interface
* MSB 64-bit half of the 128-bit EVEN L0CacheBuffer Port interface

the detection as to whether any given one of these should be enabled
is simply done by ORing the relevent sections of the 16-bit byte-enable
column line (wen / ren).  this comes directly from the "en" lines
from DataMerger.

* half (8) of the Datamerger byte-enable lines will go to enabling
  one of the 64-bit Wishbone interfaces
* the other half (8) will go to the other one.

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