[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #88 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #86)
> hi michael, apologies i couldn't help it, i did some of the TODO
> comments on trap main_stage:
> 
> -        # TODO: MSR (into srr1)
> +        # take a copy of the current MSR in SRR1
> +        comb += msr_copy(srr1_o.data, msr_i) # old MSR
> +        comb += srr1_o.ok.eq(1)
>  
> also i wandered through the 3.0B PDF and found the section that
> covers "Program Interrupts" - Book III 7.5.9
> 
> i therefore added these defines:
> 
> PI_TRAP = (63 - 46)    # 1 if exception is "trap" type
> 
> and changed the setting of the relevant SRR1 bit to use that definition:
> 
>                     self.trap(0x700, cia_i)
>                     comb += srr1_o.data[PI_TRAP].eq(1)
> 
> now we have words instead of numbers when it comes to reading through the
> code.  we can see, in two lines of code:
> 
> 1. "it's a trap" (self.trap - duh). 
> 2. execution continues at address 0x700
> 3. the trap handler (in software) can read SRR1 and know exactly what to do

(In reply to Luke Kenneth Casson Leighton from comment #87)
> (In reply to Luke Kenneth Casson Leighton from comment #86)
> > hi michael,
> 
> cole!  gaah :)   names... massive headache (again) at the moment.

Hehe no problem :) I took a look at this yesterday evening, and I was going to
ask you for help because I was stuck, so, so much the better!

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