[libre-riscv-dev] [Bug 360] New: move RS to 1st or 2nd operand in CSV files

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=360

            Bug ID: 360
           Summary: move RS to 1st or 2nd operand in CSV files
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

we are doing this - a lot - i.e. in nearly every single Function Unit:

        # RA (or RC)
        reg3_ok = yield dec2.e.read_reg3.ok
        reg1_ok = yield dec2.e.read_reg1.ok
        assert reg3_ok != reg1_ok
        if reg3_ok:
            data1 = yield dec2.e.read_reg3.data
            res['a'] = sim.gpr(data1).value
        elif reg1_ok:
            data1 = yield dec2.e.read_reg1.data
            res['a'] = sim.gpr(data1).value

if instead the CSV files *specified* that RS was in position (read_reg1)
*already*, this would no longer be necessary.

the same thing applies to ShiftRot - except this time RS and RB should
be actually *swapped over*.

this is quite a big change as it affects every single Function Unit,
unit test, and formal proof.

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