[libre-riscv-dev] daily kan-ban update 09jun2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jun 9 18:44:23 BST 2020

On Tue, Jun 9, 2020 at 6:21 PM Jacob Lifshay <programmerjake at gmail.com> wrote:

> yesterday:
> not much

:) rest is good

> today:
> working on mul and div units -- they will most likely increase the core's
> gate count by a large amount, particularly the div pipeline, since it's
> designed for high performance, not as much for low area.

hm hm well as long as it is below 45k LUTs we should be good.  last
resort there is always the microwatt div algorithm, which i noticed in
its FSM has the option to skip large batches of zeros (8 at a time).
personally i hope it fits, hmm it should be easy to check, with
this is for test_div_pipe_core_bit_width_8_fract_width_4_radix_2.il

=== top ===

   Number of cells:               3411
     CCU2C                         461
     L6MUX21                       116
     LUT4                         1777
     PFUMX                         539
     TRELLIS_FF                    518

that's a very small one, though, isn't it?  bit-width of 8?

> Also, I saw the new *inter-core* speculative execution vulnerability in
> Intel processors, the previous ones were mostly intra-core.

oh no!  i don't know whether to laugh, start to feel sorry for them,
or look it up and make sure we don't make the same mistake.  probably
all of those :)


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