[libre-riscv-dev] Minerva L1 Cache
yimmanuel3 at gatech.edu
Mon Jun 15 17:57:22 BST 2020
> maybe. we will have to evaluate it. as i explained in the crossover
> message there are other higher priority design requirements that are unique
> and specially required for the design.
I watched the video and read through the pages.
I understood high level what is going on - the details are
not entirely clear to me at this stage.
At some point, I can imagine that you’ll want to connect
up the memory systems. How much labor do you think
is needed for this? Assuming I’m free starting at the end of July,
It would probably take me a couple weeks to catch up to speed
on the intricacies of the scoreboard.
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