[libre-riscv-dev] daily kan-ban update 17jun2020

Cole Poirier colepoirier at gmail.com
Wed Jun 17 21:35:42 BST 2020

On Jun 17 2020, at 6:41 am, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> yesterday:
> * created an initial test instruction memory SRAM
> * got a unit test running that reads from it

Woohoo! Congratulations! Very cool to see how quickly the modules are
being integrated to make the simple core more realistic.
> today:
> * get the simulator (ISACaller) to read its instructions from a
> simulated memory
> btw alain is getting 5.0.6 bugzilla running on apache2 via a proxy
> redirect so that the REST API works, and we can actually finally
> actually have a kan-ban board to look at.

Very good to hear, looking forward to using it once it's all set up.


* Met with Yehowshua, Luke, Dan about investort pitchdeck
* Finally got most of my tasks organized, started adding appropriate
bugs to the bug tracker


* finish adding bugs for tasks from conversations fro my personal
organizer into the bug tracker, then adding links to them to my personal
wiki page. Moving forward this process will run in reverse, adding a bug
to the bug tracker then planning specific times to work on it in my
personal organizer/agenda.

* LibreSOC/OpenPOWER Sync Mkll (what does Mkll stand for by the way, Luke?)

* Migrating all libre-soc-dev bugs other that libre-soc-org bugs to new
mailing list default cc of libre-soc-bugs

* Trap pipeline pseudo code so that TRAP insns can be called by the simulator

* Review bugs/issues Dan has added on his github for the early stages of
the Elm SPA

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