[libre-riscv-dev] libresoc memory architecture

[Luke Kenneth Casson Leighton]

On Wednesday, June 24, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:

> One note:
> conventional wisdom is that once your outside of the stuff that's local to
> a core (and even some before then), all interfaces are non-speculative.
> That also greatly simplifies the required hardware support for spectre,
> since otherwise it's very easy to leak data from one core to another
> through shared speculative hardware.


there was a paper somewhere that yehowshua srnt about this, about L1, L2
and MMU and SMP design that did properly deal with this.

the basic principle if i understand it was that each object had a "mini
cache" in front of it.  L1 had a mini L1 cache, L2 likewise and so on.

these minicaches were speculative-capable and the thing they were fronting
for was not.

in other words the minicache is compliant with the offer-exchange-complete
protocol and the thing behind it is take-it-or-leave-it.

in _other_ words the minicache stores the *offers* (which contain both
address *and* data) and the thing behind it stores the "completions".

in this way, because the minicache contains the data at the "offer" phase
no speculative operations EVERRRR hit the thing behind it.  no evictions,
no resource utilisation, nothing.

consequently there is no opportunity for speculative harm.

l.



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