[libre-riscv-dev] daily kan-ban update 27jun2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Jun 27 18:19:07 BST 2020
* messing with Load/Store converters and unit tests (thanks to michael)
focus was to get minerva LoadStoreUnitInterface compliant tests working
* got LoadStore through *PortInterface* unit tests working.
we now have *six* different unit tests for different memory
configurations and combinations of interfaces, slowly working up from
small Test Memories to full wishbone connectivity.
whilst the simpler ones do not have any kind of stalling or error
handling, at some point, particularly when connected to a common
wishbone bus (which can be busy), this large batch of unit tests comes
into its own as the last thing we want is to be forced to compile 10
megabytes worth of processor just to test if the memory interface
rest of day:
* maybe try putting new Configureable PortInterface classes into test
core, see what happens when connecting to wishbone
* maybe try adding the minerva L1Cache code to the unit tests.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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