[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #90 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #89)
> ok so i added two new signals to Decode2Execute1Type, called
> traptype and trapaddr.  the idea is that rather than get main_stage.py
> to *hard-code* what type of trap it is, and *hard-code* the address to
> jump to, the *decoder* says what the trap type is, and where to jump to.
> 
> in this way we can detect interrupts, privileged instructions, and so on,
> in the *decoder*.
> 
> unfortunately... this means that the decoder needs access to MSR.  whoops.
> this is slightly unfortunate, because up until now, PowerDecoder2 needed
> absolutely nothing - no information *at all* - about the "state".  didn't
> need the PC, didn't need anything.
> 
> 
> +        with m.If(op.internal_op == InternalOp.OP_TRAP):
> +            comb += e.traptype.eq(TT_TRAP) # request trap interrupt
> +            comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
> +
> +        return m
>  
> +        # privileged instruction
> +        with m.If(instr_is_privileged(m, op.internal_op, e.insn) &
> +                  msr[MSR_PR]):
> +            # privileged instruction trap
> +            comb += op.internal_op.eq(InternalOp.OP_TRAP)
> +            comb += e.traptype.eq(TT_PRIV) # request privileged instruction
> +            comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)

Very cool. Can you comment on the implications of the decoder needing access to
MSR here? or is that meant to be a comment on a different bug report. If so,
please link it here, because I'd like to understand the decoder better. Going
to finally get to try the learning process involving gtkwave today!

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