[libre-riscv-dev] daily kan-ban update 01jun2020

[Luke Kenneth Casson Leighton]

yesterday:

* got MultiCompUnit functional when interacting through the pipeline
API with the ALU that it manages.  (MultiCompUnit now qualifies as the
2nd or 3rd most complex piece of software engineering i've ever
tackled, in 30 years.  yes i keep a list.  with one exception, all of
the others involve SQL)
* got the ALU MultiCompUnit test working (found several bugs)
* got the Logical MultiCompUnit test working (found one bug)
* got the Condition Register MultiCompUnit test working (found two bugs)
* got the Branch Register MultiCompUnit test written

this morning:

* answered Marketnext about the upcoming Hackathon.  they got it
(which is great) - namely that the process we follow also applies to
Marketnext entrepreneurs just as much.
* got the Branch Register MultiCompUnit test working (swapped the
order of SPR1/SPR2)

today:

* Shift-Rot MCU (should be about 15 minutes)
* start looking at connecting MCUs to regfiles.

upcoming tasks (soon to be blockers) and blockers:

* TRAP, SPR and SYS pipelines (we need volunteers to work on these)
* MUL and DIV pipelines (Jacob)
* Interfaces for the 180nm ASIC.

l.

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68