[libre-riscv-dev] Named Records in nMigen

[Luke Kenneth Casson Leighton]

On Mon, Jun 1, 2020 at 7:29 AM Yehowshua <yimmanuel3 at gatech.edu> wrote:
>
> Does anybody know if its possible to have a named records

Record.  give each bit (or bit range) a name and it is possible to
either assign (eq) to each bit (or bit range) *or* to the entire
thing.  bear in mind caveat (1) below.


> or subsignals in nMigen?

as Jock says: python slice, and use an Enum or a defined (named) constant.

bear in mind the following:

* Record is treated as a sequence of bits... *not* a sequence of
fields. several people objected to this, and whitequark to her credit
finally listened. however the replacement for Record is still under
development.

* RecordObject was created to allow for an over-ride of the behaviour
of Record, providing us with the ability to actually have something
more like python OO behaviour.

* you can use Cat on *BOTH* sides of the equation.  *PAY ATTENTION* to
the LSB-MSB ordering.  Cat is in *LSB* sequential ordering starting
from the 1st argument, where numbers, in the ENGLISH LANGUAGE, start
from the *MSB*.

   m.d.comb += Cat(mysig[0], mysig[5], mysig[6]).eq(Const(0b110, 3)

is equivalent to:

   m.d.comb += mysig[0].eq(0)
   m.d.comb += mysig[5].eq(1)
   m.d.comb += mysig[6].eq(1)

* to cope with both POWER9 LE/BE and also to help with ISA field
decoding, we created something that allows for "remapping" of fields.
it's called SignalBitRange.  this allows you to *remap* a sequence of
bits to completely different ranges.

l.