[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #21 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
 comb += self.o.msr.data.eq(Cat(b[63:31], b[26:22], b[15:0]))

this says "concatenate bits and put thrm into the LSBs of MSR".

look again at the VHDL.  it says, "transfer 3 sets of bits into their exact
same corresponding bit places.

also, python numbering is start:end+1

you have specified end:start

so the ranges are 0:16
22:27
31:64

make 3 separate assignments ok?



 comb += self.o.msr.ok.eq(a)


the ok field is 1 bit, saying "this reg is to be written".  by placing the LSB
of a into it (because msr.ok is only 1 wide), you end up with random situations
where the MSB will randomly get written.

msr.ok should be set to 1, to gyarantee it will be written.


also remember to translate this bit:

          if c_in(MSR_PR) = '1' then
 131                         ctrl_tmp.msr(MSR_EE) <= '1';
 132                         ctrl_tmp.msr(MSR_IR) <= '1';
 133                         ctrl_tmp.msr(MSR_DR) <= '1';



OP_SC looks great.

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