[libre-riscv-dev] Handling POWERVec Instructions

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jun 11 22:52:06 BST 2020

On Thu, Jun 11, 2020 at 10:21 PM Yehowshua <yimmanuel3 at gatech.edu> wrote:
> Just spitballing hereā€¦
> But what we could do is trap and then scan the next 1024 instruction in software and JIT to SimpleV.

it sounds reasonable enough to me.  could be done as a parallel
project in a simulator.


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