[libre-riscv-dev] Introduction

Yehowshua yimmanuel3 at gatech.edu
Mon Jun 15 21:16:31 BST 2020

>  I have limited experience with Assembly and Verilog as well as
> extensive experience with c/c++ but I am excited to learn Nmigen and hope
> to contribute to the Power Core


I’ll let Luke follow up a bit, but also do subscribe to the LibreSOC misc mailing list below[1].
Reason being is that I and others can help newcomers with more specific FPGA, RTL,
and nMigen concepts allowing us to keep the main dev mailing list lower traffic.

And as always, Welcome!


[1]: http://lists.libre-soc.org/mailman/listinfo/libre-soc-misc

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