[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
TODO: add OP_SC line but not exactly like it is done in microwatt:
it has to go in extra.csv so as to be able to detect (and exclude) scv.
this through bit 1 (actually bit 30 sigh) "if e_in.insn(1) = '1' then"

     17 =>       (ALU,    OP_SC,        NONE,       NONE,        NONE, NONE,
'0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0',
'0'), -- sc

so this would be something like:

17 in binary ------  bit 30 here
010001------------------------1-,TRAP,OP_SC,....,sc,NONE

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