[libre-riscv-dev] Understanding the LibreSOC core

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Jun 8 19:24:12 BST 2020

On Mon, Jun 8, 2020 at 7:03 PM Sanjay Menon <sanjayamenon.mec at gmail.com> wrote:
> Hi,

hi! :)

> Currently making a little progress on the nMigen tool.

excellent. you understand gates (and verilog) already, so it should be
pretty straightforward.  Cesar i think got used to nmigen in around,
maybe 2 weeks?  it took me about that long.

> Got to see some interesting things been discussed on the Alexa IOT pitch
> for LibreSOC.
> I have a few questions for you guys
> 1.Where do I start if I were to check into the LibreSoC source code?

ha, ok, hum, bear in mind it's 75,000 lines, ok?  so i do recommend:
be patient, both with us and with yourself.  you've got nmigen already
(and yosys? and symbiyosys? - you only need symbiyosys and its
dependencies if running the formal proof tests)

have you followed the "quick peek at the code" on the frontpage?
https://libre-soc.org/ if so, you have the 3 key repositories, and you
could, for example, run the simple_core.py test that i posted about,
yesterday.  you *may* need to re-run pywriter.py though - see the
top-level Makefile

you can also just browse the source code directly online.  here's
core.py for example:

and its unit test:

if you use vim, i recommend also "apt-get install exuberant-ctags",
then in each top-level directory where you work from, run "ctags -R".
you can then jump to any definition of any variable, class or
function, by putting the cursor on it and pressing "Ctrl-]"

> 2. Is this SoC in any way similar to the Xilinx ZYNQ architecture?.
> Where the ARM embedded processor would be replaced by PowerPC and the
> reconfigurable logic is converted to a GPU like entity, together forming a
> heterogeneous SoC.

ah no.  it *really is* an actual POWER9 core, where the plan is to
*extend* the POWER9 ISA (safely, and with careful mentoring from IBM
and the OpenPOWER Foundation), to add SimpleV vectorisation, YUV2RGB
instructions, Texture Interpolation instructions, and a shed-load

those instructions *actually* run as *CPU* instructions, and we will
beef up the internal architecture to the point where it can cope with
the significant data and computational demands of executing GPU
workloads.  this is why we are going with a multi-issue OoO execution
engine, because it's the... "sane" way of dealing with the mixed
workloads of both sequential and parallel operations.

that is what being a "hybrid CPU-GPU-VPU" is all about.  it's very
much *not* about "farming off GPU workloads to elsewhere" - the
complete opposite is true.

> 3. Do you plan to run the SoC on an FPGA for prototyping and testing
> purposes?,

yes absolutely!  there is a EUR 10,000 budget allocated to this task:

> or are you using some other methodologies?

i'd also like us to be able to use coriolis2 simulation.  this is
right at the gate level, about as close to the GDSII files as you can
get without actually paying for masks.

although it will be INSANELY slow, it will allow us to check that the
HDL has actually been properly translated into what we expect to be


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