[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Jun 7 02:42:35 BST 2020


--- Comment #69 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
see https://bugs.libre-soc.org/show_bug.cgi?id=325#c8

there, the only difference between OP_TRAP and that code is: one of the bits of
SRR is changed (to indicate "priv execution")

we can pass that in as a flag to CompTrapOpSubset, and change the instruction

illegal instruction trap happens. ta-daaa

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