[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #68 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
actually... cole, can you do the same thing as i just did with msr_check_pr()
create a function called trap(m, addr, nia)?

except this time it is a member function of the class, so trap(self, m, addr,
nia)

and just as you see i redid comb=m.d.comb in msr_check_pr, repeat/copy the
convenience variables that allow you to set self.o.nia etc etc

the reason for making this function is because you can see it is used twice
already.

also i am thinking it may be a good idea to add the address (0x700, etc)
actually to the trap_input_record and pass it in from the *decode* phase.

that would allow us to do exceptions in a micro-code fashion, and also when it
comes to illegal instructions or privileged ones, in the *decode* phase
(PowerDecoder2) we *CHANGE* the opcode from whatever it is from the incoming
instruction, into an OP_TRAP, set the trap address to 0x700 (or whatever)
manually, and let the trap pipeline execute it.

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