[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #67 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #64)
> (In reply to Luke Kenneth Casson Leighton from comment #62)
> > > Or is this  the one that is
> > > generated from parsing the csv files?
> > 
> > yes.  hence the need for the pseudocode.  until that exists there *is* no
> > mfmsr (etc) to test against!
> > 
> > in this case even the TRAP function has to be written.
> > 
> > this would (in python) move the SPRs about, set NIA to 0x700 blah blah.
> 
> This makes so much sense now and is very, very cool! Especially in light of
> your comments from comment #59 "actually i don't [completely understand
> pywriter.py]: it has been several months, and i wrote it very fast,
> to perform a minimal job!"
> 
> Regarding your comment on today's kanban daily update, "put a preliminary
> version of mtmsr into the mdwn for Cole to check", how do I go about
> checking the mdwn pseudo code with the emulator and the nmigen module?

in the libreriscv submodule first to "git pull origin master" - watch out
because submodules are a pain - then you can generate the emulator code.

run pywriter.py (see top-level Makefile).  then - and only then - will
the simulator "understand" mtmsr.

you can inspect the results by looking at... errr... what did we say
it was added to?  sprset.mdwn?

so... pywriter.py will.. err.. put that into... 1sec....
soc/decoder/isa/sprset.py

[btw do *NOT* "git add" that to the repository (it's auto-generated.  we
 do *NOT* add auto-generated files to the git repository, because they
 change).]

example:  mcrxrx, from the sprset.mdwn file

* mcrxrx BF

    CR[4*BF+32:4*BF+35] <-  XER[OV] || XER[OV32] || XER[CA] || XER[CA32]

---> is translated to, in sprset.py --->

    @inject()
    def op_mcrxrx(self, CR):
        CR[4 * BF + 32:4 * BF + 35 + 1] = concat(XER[OV], XER[OV32], XER[CA],
XER[CA32]
            )
        return (CR,)


at that point, you *should* be able to add something to
soc/fu/trap/test/test_pipe_caller.py in class TrapTestCase

which i see you deleted all the unit tests (i usually leave one
in there on cookie-cutting so that it's less typing when it comes
to creating one.  now you will have to re-open one of the
test_pipe_caller.py files to cut/paste an example from.  this is
more work for you)


here's the thing: it is highly likely that op_trap() from sprset.py
will fail.  this because it's literally the first time that the emulator
has ever seen the "trap" instruction, and that code also has to be written.

do not let this stop you from actually writing the unit test!

the unit test *is* the way to highlight that the code needs to be written!
[this is called test-driven development]
https://en.wikipedia.org/wiki/Test-driven_development


> > so the translator pushes an extra +1 out on the "end" of the slice.
> > 
> > you saw that when doing bperm.
> 
> Thanks this helps me understand the 'problem' even better than I did from
> your earlier comments. Also very ingenious.

just lazy :)

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