[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Jun 8 15:10:44 BST 2020


--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
-                comb += ov_o.data[0].eq((add_o[-2] != a[-1]) & (a[-1] ==
-                comb += ov_o.data[1].eq((add_o[32] != a[31]) & (a[31] ==
+                # 32-bit (ov[1]) and 64-bit (ov[0]) overflow
+                ov = Signal(2, reset_less=True)
+                comb += ov[0].eq(calc_ov(a[-1], b[-1], ca[0], add_o[-2]))
+                comb += ov[1].eq(calc_ov(a[31], b[31], ca[1], add_o[32]))
+                comb += ov_o.data.eq(ov)

michael i believe the former code may have been incorrect, one of the tests
should have been using the carry (32/64) flags rather than the MSB of a?

also the OV32 handling in the simulator is missing, i will try to add

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