[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #28 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #22)

> Thanks. I'm not sure how to tranlate c_in

err... errr... that means *sigh* having to look at the CSV files and see if
reg c can be moved to reg a, for MTMSR.

b _definitely_ needs to be in position "b" - so that means that in OP_RFID
this needs to be b not a:
     comb += self.o.msr.data[stt:end].eq( --->a<---- [stt:end])


> and in OP_MTMSR this seems to be
> done by just:
> 
> ```
> comb += self.o.msr.data.eq(a)
> comb += self.o.msr.ok.eq(1)
> ```
> 
> Is this correct?

it is... but we need to check minor_31.csv - ah:
0b0010110010,ALU,OP_MTMSRD,NONE,NONE,RS,NONE

that's wrong.  it says "RS goes into reg c" and if you look at
fu/trap/pipe_data.py
we don't *have* an rs.

so i'll go ahead and change that to:

0b0010110010,ALU,OP_MTMSRD,RS,NONE,NONE,NONE

and that will put RS into *a* (which we have)

gimme 1 sec...

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