[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Jun 3 02:41:06 BST 2020


--- Comment #29 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #28)

> and that will put RS into *a* (which we have)
> gimme 1 sec...

commit 7e32307f763f693a405a5d1691fb23894bcd3be3 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Jun 3 02:39:29 2020 +0100

    update submodule for ISA tables

done, do make sure to do a "git submodule update" and make sure
"git submodule" reports this:
1970241a6db97d4ace1e053e72f2a3d9462e98b2 libreriscv

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