[libre-riscv-dev] libresoc memory architecture

[Luke Kenneth Casson Leighton]

so, michael: throughout all of what i described, PortInterface is the
common factor right up until connecting to Minerva LoadStoreInterface.

dual splitting: PortInterface.
L0CacheBuffer: PortInterface.

everything, with each class providing additional guarantees and
functionality (such as misalignment in the case of dual splitting, and the
address checking)

therefore we can simply bypass *all* of those for testing purposes and
*incrementally* add in the additional functionality after unit tests have
been written that confirm the blocks in isolation.

the key piece that is currently missing is a converter class between
PortInterface and Minerva LoadStoreInterface.

this will require a LenExpand instance (see LDSTSplitter and
TestMemoryPortInterface in pimem.py) to convert the binary data_len and the
LSBs of the address into a bitmask.

what is also missing is a unit test that is compliant with the
LoadStoreInterface, connecting to a nmigen Memory, that does *NOT* use
Wishbone (ignores the wb record entirely).

close examination of Minerva core.py shows that the core **ONLY** interacts
through the LoadStoreInterface **NOT** the wishbone interface directly.

i.e. both minerva BareLoadStoreUnit *and* CacheLoadStoreUnit are in control
of and responsible for use of the wishbone bus record... **NOT** the core.

therefore we can dramatically reduce what is incrementally needed by first
ignoring entirely the Wishbone interface.

so could you please start with the following:

1) a TestMemoryLoadStoreUnit that contains a TestMemory instance and
presents a LoadStoreInterface.

2) a unit test for that

3) a PortInterface to LoadStoreInterface converter.  feel free to cheat and
ignore whatever is needed to get it "working".  use TestMemoryPortInterface
as the template. it uses LenExpand so does the conversion to x_mask.

assume initially that the data path from PortInterface is 64 bit not 128
bit.

4) a unit test for that


then it *should* be trivial to:

5) connect Pi2LSI to TMLSU and demonstrate it works

6) copy or better provide an option in simple/core.py and issuer.py to use
the Pi2LSI->TMLSU route instead of TestL0CacheBuffer.


after *that* we can use parts of the unit tests (4) to begin testing
BareLoadStoreUnit (and CacheLoadStoreUnit), after connecting them to Harry
Ho's nmigen-soc sram.py

after *that* we can go back to core.py and issuer.py and add *another*
option to allow BareLoadStoreUnit and CacheLoadStoreUnit to be selected,
next to L0CacheBuffer (again, via the Pi2LSU converter)

in addition we can create a standalone test which brings in L0CacheBuffer
into the mix:

L0CacheBuffer -> Pi2LSU -> TestMemoryLoadStoreUnit / BareLoadStoreUnit /
CacheLoadStoreUnit.

and then fiiiinally back at core.py and issuer.py drop that chain into
place.


along the way we can look at how to connect PortInterface 128 bit to dual
64 bit LoadStoreInterfaces, once the basics are in place (somewhere after
step 6)

all incremental development so that any changes and additions made will be
detected immediately by way of failing unit tests.

l.



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