[libre-riscv-dev] libresoc memory architecture

[Michael Nolan]

On 6/24/20 8:21 AM, Luke Kenneth Casson Leighton wrote:
> so, michael: throughout all of what i described, PortInterface is the
> common factor right up until connecting to Minerva LoadStoreInterface.
>
> so could you please start with the following:
>
> 1) a TestMemoryLoadStoreUnit that contains a TestMemory instance and
> presents a LoadStoreInterface.
>
> 2) a unit test for that
>
> 3) a PortInterface to LoadStoreInterface converter.  feel free to cheat and
> ignore whatever is needed to get it "working".  use TestMemoryPortInterface
> as the template. it uses LenExpand so does the conversion to x_mask.
>
> assume initially that the data path from PortInterface is 64 bit not 128
> bit.
>
> 4) a unit test for that

Ok, this seems reasonably straightforward. I'll give it a go.

--Michael