[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #49 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #48)
> just did some updates/comments so we can see what's going on, in english.

Appreciated, significantly clearer than it was before. Looking at the code, it
seems to be in line with the VHDL in the comments. One question, what does '#
XXX which bit?' on line 147 refer to?

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