[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #50 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #46)
> Ok. I think now the nmigen should match the microwatt VHDL, however, there
> may be small errors as you made some modifications but left others for me to
> fix, and I got confused about some of your comments re a_i, b_i, but I did
> my best to interpret your comments while reading, line-by-line the vhdl from
> the comments.

microwatt decided to use a_in, b_in and c_in as the input lines for *SPRs*.

we are not going to do that.

therefore all places where SPRs are inputs, the names need to *be* SRR0,
*be* SRR1, *NOT* a_i, b_i, c_i.

however - some of the instructions *DO TAKE REGISTERS AS INPUT*.
see section 5.4.3, "mtmsr" for example: this takes a *REGISTER* (RS)
as the input, and moves it to the MSR (as output)

whereas OP_RFID, you can see clearly the pseudocode says:

  nia <= SRR0
  msr <= SRR1

however microwatt has this:

  nia <- a_in
  msr <- b_in

this is obviously a design decision that WE ARE NOT GOING TO COPY.

where they must have done this:

  a_in <- SRR0
  b_in <- SRR1

and then and only then could this microwatt code succeed:

  nia <- a_in
  msr <- b_in

we are **NOT** repeat **NOT** going to re-purpose register file lanes.
we have *SEPARATE* lanes for SPRs, *SEPARATE* lanes for integer registers.

if we were to copy what microwatt have done we would need full data-routing
crossbars in front of the register file ports to get data from the SPR
register files over to the integer inputs on the TRAP pipeline.

in an out-of-order system such "hacks" creates a severe architectural problem
for
Dependency Tracking and Management.

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