[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=376

--- Comment #12 from Jacob Lifshay <programmerjake at gmail.com> ---
Assuming we're building a higher than 2W version, I think we should double the
int/fpmul to 8x32-bit per core or maybe even quadruple it to 16x32-bit and add
more cores to 8 or 16 or more cores. The div and transcendental pipelines
wouldn't probably need to be expanded since they would probably still have
enough throughput. Also, it might be worthwhile to add one more core and
disable one at manufacture time as a way to increase yield.

If possible, I think we should implement a cache-coherent memory interface over
the PCIe bus so we can just have the host's linux kernel schedule processes as
usual between the host POWER9 processor and the GPU, acting like the GPU is
just more processor cores to schedule. That will allow nice things like using
the GPU as extra CPU cores to help accelerate compile or other tasks and being
able to use Kazan without needing lots of in-kernel GPU queues and stuff.

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