[libre-riscv-dev] Understanding the LibreSOC core

[Michael Nolan]

On 6/8/20 2:55 PM, Luke Kenneth Casson Leighton wrote:
>
> ok so i ran the following yosys commands:
>
> $ python soc/simple/core.py
> $ yosys
> read_ilang non_production_core.py
> proc
> opt
> flatten
> synth
>
> and it produced this:
>
> === top ===
>
>     Number of wires:              40844
>     Number of wire bits:          93864
>     Number of public wires:        5816
>     Number of public wire bits:   58836
>     Number of memories:               0
>     Number of memory bits:            0
>     Number of processes:              0
>     Number of cells:              42932
>       $_ANDNOT_                   11780
>       $_AND_                        399
>       $_DFF_P_                     3542
>       $_MUX_                      11446
>       $_NAND_                      3272
>       $_NOR_                        567
>       $_NOT_                       2751
>       $_ORNOT_                      419
>       $_OR_                        8622
>       $_XNOR_                        35
>       $_XOR_                         99

It should fit. Running synth_ecp5 instead of the generic asic synth 
above gives me this:

3.52. Printing statistics.

=== top ===

    Number of wires:              24216
    Number of wire bits:          72752
    Number of public wires:       24216
    Number of public wire bits:   72752
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
    Number of cells:              22710
      CCU2C                          72
      L6MUX21                      1203
      LUT4                        14962
      PFUMX                        3454
      TRELLIS_FF                   3019

--Michael