[libre-riscv-dev] libresoc memory architecture

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jun 23 20:52:27 BST 2020

On Tuesday, June 23, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:

> On Tue, Jun 23, 2020, 11:27 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
> > we will need an "address-aware" system that tells us - in hardware
> > terms not in python source code terms - in *hardware* - whether the
> > address being requested will succeed/fail or not.
> Note that the PowerISA page tables contain bits that specify if a memory
> page is normal ram, read/write-combining I/O, or non-combining I/O, so we
> don't need to build special hardware decoders to determine the properties
> of a physical address.



ok, bear with me :)


> See PowerISA v3.1 section 1.6 and section
> The spec also specifies how memory should be accessed when using unusual
> methods, such as when the page tables are disabled.

 first, we need to make sure to capture those spec references, can you add
a crossref to the archives onto the architecture/cachemem page ?

ok, so the hardware function i mentioned, i had to design one that was
autogenerated by the pinmux program, when helping IIT Madras.

question: where do the PowerISA MMU tables get the information from about
which bits are IO, RAM, or other?

answer: they come from the information about the physical memory map.

question: where does *that* information come from?

answer: from the hardware-level function that is effectively a series of
range-checking comparisons that ultimately give us the desired information.

the function is quite simple and can either be statically created or it can
dynamically create a sequence of nmigen range comparisons in a python

in the bluespec work that i did for IIT Madras, the addresscheck function
was statically-generated BSV.

as we are using python we can do it dynamically in the same way that
PowerDecoder has been done.

the information you tracked down is valuable Jacob because it tells us that
the hardware function should, in a similar fashion to PowerDecoder2, return
whether the address is physical memory, IO, readonly IO and so on.

as we do not have MMU page tables (yet) we will have to read the
information directly from the Bus Decoder, for now.


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