[libre-riscv-dev] libresoc memory architecture

[Luke Kenneth Casson Leighton]

On Tuesday, June 23, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

>
> in the bluespec work that i did for IIT Madras, the addresscheck function
> was statically-generated BSV.
>

(statically generated by pinouts.py which read the specification and
created the full AXI4 slave peripheral definitions and so on.  it was
several months work)


> as we are using python we can do it dynamically in the same way that
> PowerDecoder has been done.
>
> the information you tracked down is valuable Jacob because it tells us
> that the hardware function should, in a similar fashion to PowerDecoder2,
> return whether the address is physical memory, IO, readonly IO and so on.
>
> as we do not have MMU page tables (yet) we will have to read the
> information directly from the Bus Decoder, for now.
>

correction: the function that creates the physical bus memory map that is
passed to nmigen_soc Decoder also needs to be.. etc etc.

l.


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