[libre-riscv-dev] libresoc memory architecture

Jacob Lifshay programmerjake at gmail.com
Tue Jun 23 20:02:04 BST 2020

On Tue, Jun 23, 2020, 11:27 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Tue, Jun 23, 2020 at 7:13 PM Michael Nolan <mtnolan2640 at gmail.com>
> wrote:
> >
> > On 6/23/20 2:04 PM, Luke Kenneth Casson Leighton wrote:
> > > there is slightly more to it than that however that is quite enough
> for now.
> > >
> > > any questions?
> > Great, that and the discussion on bug 393 helps quite a bit
> this one covers the "contract of sale" API.
> https://bugs.libre-soc.org/show_bug.cgi?id=397
> there *is* a potential way to do this without modifying Wishbone -
> however it means we have to use our own Bus protocol (PortInterface)
> right the way through to talking to Minerva LoadStoreInterface.
> however when it comes to using nmigen-soc Wishbone InterconnectShared:
> https://git.libre-soc.org/?p=nmigen-soc.git;a=blob;f=nmigen_soc/wishbone/bus.py;h=HEAD#l493
> we will need an "address-aware" system that tells us - in hardware
> terms not in python source code terms - in *hardware* - whether the
> address being requested will succeed/fail or not.
> this means that we need a *hardware* function which respects / mirrors
> the nmigen_soc WB Decoder "memory_map":
> https://git.libre-soc.org/?p=nmigen-soc.git;a=blob;f=nmigen_soc/wishbone/bus.py;hb=HEAD#l236
> that hardware function will tell us - *at the offer phase* of the
> Contract-of-Sale - whether the request WOULD succeed IF allowed to
> proceed to exchange-and-complete.
> this is not as straightforward as a "simple range of addresses"
> because in the case of DRAM (connected over LiteDRAM) the range of
> physical addresses that will succeed will *depend on available
> external RAM chip size*.

Note that the PowerISA page tables contain bits that specify if a memory
page is normal ram, read/write-combining I/O, or non-combining I/O, so we
don't need to build special hardware decoders to determine the properties
of a physical address.

See PowerISA v3.1 section 1.6 and section

The spec also specifies how memory should be accessed when using unusual
methods, such as when the page tables are disabled.


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