[libre-riscv-dev] libresoc memory architecture

[Luke Kenneth Casson Leighton]

On Tue, Jun 23, 2020 at 7:13 PM Michael Nolan <mtnolan2640 at gmail.com> wrote:
>
> On 6/23/20 2:04 PM, Luke Kenneth Casson Leighton wrote:
> > there is slightly more to it than that however that is quite enough for now.
> >
> > any questions?
> Great, that and the discussion on bug 393 helps quite a bit

this one covers the "contract of sale" API.
https://bugs.libre-soc.org/show_bug.cgi?id=397

there *is* a potential way to do this without modifying Wishbone -
however it means we have to use our own Bus protocol (PortInterface)
right the way through to talking to Minerva LoadStoreInterface.

however when it comes to using nmigen-soc Wishbone InterconnectShared:
https://git.libre-soc.org/?p=nmigen-soc.git;a=blob;f=nmigen_soc/wishbone/bus.py;h=HEAD#l493

we will need an "address-aware" system that tells us - in hardware
terms not in python source code terms - in *hardware* - whether the
address being requested will succeed/fail or not.

this means that we need a *hardware* function which respects / mirrors
the nmigen_soc WB Decoder "memory_map":
https://git.libre-soc.org/?p=nmigen-soc.git;a=blob;f=nmigen_soc/wishbone/bus.py;hb=HEAD#l236

that hardware function will tell us - *at the offer phase* of the
Contract-of-Sale - whether the request WOULD succeed IF allowed to
proceed to exchange-and-complete.

this is not as straightforward as a "simple range of addresses"
because in the case of DRAM (connected over LiteDRAM) the range of
physical addresses that will succeed will *depend on available
external RAM chip size*.

 l.