[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #51 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #50)
> if you feel it does not take a long time to "fix" alu_hier.py ALU classes
> please do go ahead.

One more thing. These test ALUs are non-pipelined, right? I mean, they take a
finite number of cycles to sequence through their stages, but are not able to
accept a new operation, each cycle, meanwhile, right?

In this case, I think setting ready_o combinatorially, based on valid_i being
high, and the sequence counter being zero, is enough. This will even keep
ready_o from activating if valid_i is high and the ALU is still busy. Will
check if it works.

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