[libre-riscv-dev] daily kan-ban update 28jun2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Jun 28 15:45:03 BST 2020

hooraaay, got it working.  the BareLoadStoreUnitInterface needed a
pair of valid signals to be set, rather than just the one.

simple/test/test_issuer.py passes its unit tests (including LD/STs)
with the test bare wishbone memory module.  this is an important
milestone as the next step is to connect to an external wishbone bus
rather than a simple internal one.


More information about the libre-riscv-dev mailing list