[libre-riscv-dev] more pipeline instructions needed

[Luke Kenneth Casson Leighton]

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/trap/main_stage.py;h=92112e612960179fac1fdda6398ac8eeb91305be;hb=HEAD

we need SPR, TRAP and SYS pipeline instructions.  does anyone want to help
with these?

l.



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