[libre-riscv-dev] [Bug 377] possible bug in Simulator Mem ld/st function

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Jun 14 00:52:09 BST 2020


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i think i got it.

nmigen memory write port, if you specify a granularity argument to cut the SRAM
into bytes, writes those bytes in *big* endian order.

however if you read the same interface with a single read-enable line, the
answer comes back in *little* endian order.


i am however much preferring thinking in LE terms when it comes to memory
layouts and byte addressing.

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