[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #58 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #57)
> (In reply to Luke Kenneth Casson Leighton from comment #56)
> > it may be because "now" is set at the default action.  i have yet to work
> > out how to detect combinatorial loops.  there may be something that can be
> > done using yosys synth, michael showed me something a couple weeks ago.  ltp
> > command?
> 
> Found it manually, staring from valid_o, and changing comb to sync along the
> way. Interesting debug experience.

i've done that before :)

> I don't really recall being much afflicted by this sort of issue. But then,
> I normally try to avoid using latches as much as possible, this may be the
> reason.

yyeah they're not a "normal" way to do FSMs.  however with some aspects being
combinatorial and some being sync, we can't use "standard" techniques.

nicely done.  test_core.py still works, which is important.

-- 
You are receiving this mail because:
You are on the CC list for the bug.