[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #56 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #55)
> (In reply to Luke Kenneth Casson Leighton from comment #54)
> > oh wait... that's a *combinatorial* ALU?  iinteresting.  i wonder
> > what that could be used for.
> 
> Well, the ALU output is already latched in MultiCompUnit. Maybe having
> another output register, inside the ALU itself, is redundant?

ah right yes i understand, now.

yes, absolutely.  the only reason for the latch, inside the test ALU, was to
simulate the concept of a pipeline stage.

however you are absolutely right: with both the incoming src regs being
latched, and the outgoing result being latched also by MultiCompUnit, it is not
necessary ro latch inside alu_hier.ALU as well.


> 
> > hmmm i tried putting OP_NOP in there, and both compunit1 and parallel
> > locked up.  this tends to indicate a combinatorial loop.  any clues?
> 
> I see. I'm looking into it.

it may be because "now" is set at the default action.  i have yet to work out
how to detect combinatorial loops.  there may be something that can be done
using yosys synth, michael showed me something a couple weeks ago.  ltp
command?

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