[libre-riscv-dev] first version of test issuer is functional

[Luke Kenneth Casson Leighton]

On Wed, Jun 17, 2020 at 12:30 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> to be able to run programs in a loop (and have them verified) it is
> necessary to first to go back to the qemu-simulator comparator
> (test_sim.py), add the capability to the *Simulator* (ISACaller) to be
> able to read instructions from a memory area, and then finally come
> back to the hardware and do the same thing.

amazingly, the following loop test in the simulator actually worked:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simulator/test_sim.py;h=95d5c75ff0b2761ae4845f2e3fd1c8e036442e03;hb=HEAD#l217

(well done michael for making that possible!)

i'm just tidying up the simulator a bit, getting it to use an
instruction "memory".

then the next bit will be getting the hardware to "listen" to the PC,
executing that same loop unit test.

l.